陕西招聘信息汇总-第1页高八斗搜职

苏州创达特科技有限责任公司 半导体芯片设计工程师 (IC / ASIC Design Engineer)(003) Being a part of self-motivated team, you will go through the R&D and production cycle of the high-end broadband communication xDSL SOC ASIC with mixed-signal processing. You will have the opportunity to architect, implement and verify complex communication system modules and interfaces. Responsibilities are, but are not necessarily limited to the following: ---Implement data protocols such as ATM and Ethernet, as well as various interfaces such as UTOPIA interface, POS-PHY interfaces, MII, RMII, SMII, and SERDES. ---Architect and implement complex SOC systems such as DMA controller, bus arbitrator, memory controller. ---As a team, working on all stages in the ASIC design flow including DFT, timing analysis, floorplanning, ECO, silicon bringup, and ATPG test support. Minimum Qualifications： ---Bachelor degree with 3+ years, Master Degree with 2+ years related experience ---Good communication skills and proven ability to work well within a team. ---Strong RTL logic design and verification skills. ---Verilog is required. VCS, DC Ultra, Primetime experience desirable. ---Previous experience in Microprocessor Design, SOC design, or Networking ASIC design such as Ethernet, MAC, RMII etc a plus. ---Previous experience in working with SMIC shuttle or full-mask tapeout a plus. 作为公司积极创新的芯片设计团队一员，您将会经历高端模数混合宽带通讯xDSL SOC芯片的研发和生产周期。您将有机会去架构，实现，和验证复杂的各种不同的大规模集成电路通讯系统和接口设计。 你的工作包括但不局限于以下责任: ---负责实现ATM和Ethernet等数字通讯协议链，以及不同的网络接口设计，例如UTOPIA，POS-PHY，MII， RMII， SMII，以及SERDES等等。 ---参与架构和实现复杂的SOC系统，以及包括DMA控制器，总线裁决中心，和内存控制器等等具体模块的实现和验证。 ---作为团队一员，共同负责芯片流片过程，包括synthesis, DFT, timing analysis, floor-planning, ECO, ATPG测试，芯片上电测试等等。 最低要求: ---相关专业经验, 本科3年以上，硕士2年以上。 ---极强的交流能力和团队合作精神。 ---极强的RTL逻辑设计和验证能力。必须熟练掌握Verilog编程。 ---如有VCS， DC Ultra，Primetime等等的Synopsys或Cadence经验更好。 ---有在处理器设计，SOC设计, 或例如Ethernet，MAC，RMII等等网络方面的经验更好。 ---如有在SMIC 的MPW或Full Mask流片的经验 工作地点：苏州工业园区 不限面议苏州工业园区国际科技园C504