成都威斯达芯片有限责任公司<br>DAV DE 影像数字电路设计工程师<br>工作职责：<BR>- 用EDA工具进行消费类电子产品芯片的设计<BR>- 芯片设计，调试，综合，时序分析及验证，以及仿真测试平台的搭建和系统级验证等。<BR>职位基本要求：<BR>- 电子工程、通信工程、微电子、应用数学或相关专业本科以上（含本科）学历；<BR>- 良好的团队合作和沟通能力<BR>- 良好的英文写作能力，英语四级425分以上；<BR>职位技能要求：<BR>- 熟悉数字电路，图像及信号处理；<BR>- 熟悉C/C++/MATLAB语言；<BR>- 有一定的VHDL/Verilog 语言编程经验<BR>- 了解ASIC/FPGA设计流程及使用工具<BR>Responsibilities: <BR>- Responsible for consumer product oriented digital IC design with EDA tools;<BR>- IC design, debugging and verification, static timing analysis and synthesis, test bench design and system level validation, and designing chip for ATE A university degree in electronics engineering, communication engineering, microelectronic, applied mathematics or equivalent;<BR>- Team work and good communication skills<BR>- Good English written skills with the ability to convey important information in reports and design documentation. 425 marks or higher in CET 4;<BR>Plus Requirements:<BR>- Proficient in digital circuit design, image and signal processing;<BR>- Strong experience in C/C++/MATLAB language <BR>- Experience in VHDL/Verilog language<BR>- Proficient knowledge in the flow and tools for ASIC/FPGA design; 注明: 简历请勿以附件形式发送,请写出简历来自哪个招聘网站.不限

成都威斯达芯片有限责任公司<br>MCU DE 单片机数字电路设计工程师<br>职位描述:<BR>-与客户进行沟通并定义单片机的产品规范；<BR>-使用诸如Cadence和Synopsys的EDA工具实现逻辑设计；<BR>-准备test patterns和逻辑仿真实现设计验证；<BR>-分析设计的时序、代码覆盖率和故障覆盖率；<BR>-填写设计检查表并参与设计检查；<BR>-在装配完成后评估及调试新的单片机芯片；<BR>-协助系统工程师完成故障分析并为客户提供技术支持； Responsibility:<BR>-Deal with customers and define new MCU product specification;<BR>-Perform logic design by using EDA tools such as Cadence and Synopsys;<BR>-Perform design verification by preparing the test patterns, performing logic simulation;<BR>-Analyze the design timing, code coverage and fault coverage;<BR>-Fill in the design checklists and participate in design review;<BR>-Evaluate the new MCU product after fabrication;<BR>-Assist system engineers for failure analysis and provide technical support for customers; 职位要求:<BR>-电子工程本科及以上学历；<BR>-熟悉Verilog HDL和EDA工具（Cadence/Synopsys）方面完备的知识；<BR>-拥有逻辑设计经验；<BR>-良好的沟通技巧，英语要求CET4;<BR>Requirements:<BR>- Bachelor degree or above in Electronics Engineering;<BR>- Sound Knowledge in VERILOG HDL and EDA tools (Cadence/Synopsys);<BR>- Logic design experience;<BR>- Good communication skills, English language with CET 4; 注明: 简历请勿以附件形式发送,请写出简历来自哪个招聘网站.不限