富士通微电子(上海)有限公司<br>(Sr.)IC Design Erg. (STB&PMP)(高级)设计工程师(STB&PMP)<br>Responsibility:<br>As a part of Fujitsu Microelectronics, Shanghai, Co. ltd, IC Design Centre Product team is to work on design, to provide time-to-market development of competitive Product. <br>The responsibilities & authorities of IC design engineer are product oriented digital IC design, detail as below:<br>1)Synthesizable RTL level design and coding;<br>2)Design verification and debug, integration of IP into a large system-on-chip;<br>3)Assist with synthesis and static timing analysis;<br>4)Test bench design to assist in system level validation, and designing chip for ATE. <br><br>Requirements:<br>1)Bachlor, Master from Microelectronics/Electrical/Electronics Engineering;<br>2)More than 3 or 7 years working experience in IC design, in the field of video, communication, etc, as team leader for one project development is preferred.<br>3)Familiar with top-down design of digital circuits, including the Verilog-HDL hardware description, assembly and simulation;<br>4)Proficient in C, FPGA developing tools such as Xilinx & Altera;<br>5)Familiar with IC developing environments including logic synthesis, timing analysis and Verilog simulation.<br><br>职责:<br>申请人主要负责富士通微电子产品的设计,为市场的发展需求提供具有竞争力的产品。设计工程师负责:<br>1)LSI的逻辑电路设计;<br>2)IP整合,合成,验证和修正;<br>3)综合、静态时序分析;<br>4)整体验证及调试,芯片的测试等。<br><br>任职要求:<br>1)微电子/电机/电子工程或相关专业本科、硕士及以上学历;<br>2)3年或7年以上IC设计工作经验,具有视频,通讯等芯片设计经验;作为Leader开发过一个项目者更佳<br>3)熟悉数字电路正向设计,包括Verilog-HDL硬件描述、综合、仿真等;<br>4)熟悉C语言编程;<br>5)能熟练使用Xilinx与Altera FPGA开发工具;<br>6)熟悉逻辑综合,时序分析,Verilog仿真等IC开发环境。不限面议上海市延安东路222号外滩中心3102室
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富士通微电子(上海)有限公司<br>(Sr.)IC Design Egr.(DTV) / (高级)设计工程师(数字视频处理)<br>Responsibility:<br><br>As a part of Fujitsu Microelectronics (Shanghai) Co. ltd, IC Design Centre Product team is to work on design, to provide Time-to-market development of competitive Product. The responsibilities & authorities of IC design engineer is: Responsible for product oriented digital IC design: synthesizable RTL level design and coding, design verification and debug, integration of IP into a large system-on-chip, assisting with synthesis and static timing analysis, test bench design to assist in system level validation, and designing chip for ATE. <br><br>Requirements:<br><br>1. Bachelor or Master degree from Microelectronics, Electrical Engineering, Electronic Engineering, Telecommunications, etc;<br>2. 3 years of working experience in IC design, experience in image/video processing and digital TV applications a plus, especially in CVBS decoder, deinterlacing, image scaling, video enhancement, etc;<br>3. Solid knowledge of ASIC design flow, familiar with logic design, simulation, synthesis and testing; <br>4. Proficient in Verilog coding, familiar with IC design & verification tool flow with hands-on experience in DC, PT, NC-Sim; <br>5. Solid knowledge in FPGA application;<br>6. Good English communication skills;<br>7. Spirit of team working.<br><br><br>职责:<br>申请人主要负责富士通产品的设计,为市场的发展需求提供具有竞争力的产品。该工程师负责LSI的逻辑电路设计,IP整合,合成,验证和时序分析,以及系统整体验证及调试,芯片的测试等。<br> <br><br>职位需求:<br><br>1. 微电子, 电机工程, 电子工程,通讯等专业学士或硕士;<br>2. 3年IC设计行业工作经验,拥有图像/视频处理及数字电视应用经验者优先,包括在复合视频信号解码, 解隔行,图像缩放,及视频图像增强等领域的工作及研发经验;<br>3. 熟悉ASIC设计流程,包括逻辑设计,仿真,综合及测试;<br>4. 熟练使用Verilog语言编程,熟悉IC设计及验证流程,熟悉DC, PT, NC-Sim等设计验证工具的使用;<br>5. 熟练使用FPGA验证工具;<br>6. 英语交流能力优秀;<br>7. 良好的团队合作精神.<br>不限面议上海市延安东路222号外滩中心3102室
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