雅格罗技(北京)科技有限公司<br>Senior FPGA IP Design Engineer 高级FPGA IP设计工程师<br>Job Responsibilities: <br>Independently specify, design, implement, verify and document hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures. <br><br>Requirements: <br>- Ph.D., M.S. with at least 3 years of experience, or B.S. with 5 years of experience in related areas<br>- Have at least 2 years of experience in processor, memory controller, PCI, or networking equipment design<br>- Solid design experience with Verilog and/or VHDL, logic synthesis, simulation and verification tools. <br>- Have a track record of successful completion of complex design projects for at least 2 years<br>- Good programming skills in C.<br><br>Preferences: <br>- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications. <br>- Familiarity with Synopsys Design Compiler, ModelSim, Prime Time.<br>- Skillful in C, C++, shell scripts, Python, and/or Perl.<br>不限面议北京海淀区清华大学清华科技园创业大厦306
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