华信邮电咨询设计研究院有限公司<br>无线网规网优工程师<br>岗位职责 <br>1、 负责通信网络的规划与优化,网络性能指标、告警信息及升级问题的采集; <br>2、 分析性能数据及存在的网络问题,给出规划及优化工作方案; <br>3、 分析网络参数,给出参数调整意见; <br>4、 检查频率及邻区规划数据,给出调整意见;<br>5、 负责与客户进行网络维护及优化工作的沟通协调。 <br><br>任职资格 <br>1、 本科及以上学历,通信类、电子类、计算机类相关专业;<br>2、 通信行业2年以上网规网优工作经验,有电信行业工作经验者优先;<br>3、 具备丰富的电信理论知识,了解通信网络系统构架及传输原理;<br>4、 具备丰富的移动通信知识,熟悉GSM、CDMA、WCDMA、TDSCDMA的系统原理、信令流程、通信协议;<br>5、 具备良好的沟通技巧和团队协作能力,能适应长期的差旅生活。不限面议浙江省杭州市文晖路183号
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天弘电子(上海)有限公司 Celestica Electronics (Shanghai) Co.,Ltd<br>硬件设计工程师(FPGA & DSP)<br>
·The working location is in Shanghai Successful candidate would join a fast moving, international design team, act as a key member in serving various OEM leaders of communication industry in Electronic Hardware design<br>·BS degree or above in EE, at least 3 years hybrid electronic design experience<br><br>Prefer design experience as following implementation with FPGA:<br>·Xilinx Spartan/Virtex series FPGA, Altera Cyclone/Stratix series FPGA<br>·Assembly programming or driver experience<br>·FIFO, RAM implementation<br>·High speed serial interface, including LVDS, LVPECL, CML, Rapid IO<br>·Timing synchronization<br><br>Skills:<br>·FPGA design processes including programming, constraints edit, functional verification, logic synthesis, floorplan and route, timing verification<br>·DSP design experience with TI C5x or C6x<br>·Hardware description language VHDL, Verilog HDL<br>·Development tools including Xilinx ISE 6x, Altera Quartus II<br>·Familiar with development tools of CCS<br>·Simulation tools of ModelSim SE<br>·Synthesis tools of Synplicity Synplify, Synopsys Design Compiler<br></p>
不限浦东新区龙东大道3000号张江集电港一号楼701-801室; 金桥出口加工区云桥路金藏路(201206)
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